Subir Maity
Researcher and Academician
4.34 (243 reviews)
4
active courses
0
removed courses
Sep 2022
first content date
Jul 2025
last content date
2306
total students
243
total reviews
4.34
average rating
15
total content length
Courses
Designing RISC-V CPU in Verilog and its FPGA Implementation
19
students
6 hours
content
Jul 2025
updated
$19.99
